library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity counter_8bit is
    Port ( clk : in  STD_LOGIC; --тактовый сигнал
           E : in  STD_LOGIC; --разрешение работы
           WE : in  STD_LOGIC; --разрешение записи
           Q : in  UNSIGNED(7 downto 0); --выход
           D : out  UNSIGNED(7 downto 0)); --вход
end counter_8bit;

architecture BEH of counter_8bit is
    signal count_reg : UNSIGNED(7 downto 0) := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if E = '1' then
                if WE = '1' then
                    count_reg <= Q;
                else
                    count_reg <= count_reg + 1;
                end if;
            end if;
        end if;
    end process;

    D <= count_reg;
end BEH;